The bandwidth of the radio channel in telecommunications systems is getting wider and wider, from hundreds of kilohertz range in 2G to tens or even hundreds of megahertz range in 4.5G and 5G. This increase in bandwidth requires an ever increasing flexibility especially for radio receiver baseband filtering prior to analogue-to-digital conversion. Furthermore, the receiver silicon area and current consumption should be minimized as more and more receivers have to be integrated on the same chip to support diversity, Multiple Input Multiple Output, MIMO, and carrier aggregation requirements in 4G and 5G.
In order to tackle the area and power reduction requirements, several solutions of merging filtering and continuous-time delta-sigma analogue-to-digital converters (ΔΣ ADCs) have been published in recent years.
With present solutions, a feedback digital-to-analog converter DAC injects its signal at the same point where a down converted and almost unfiltered radio frequency, RF, signal is injected. This leads to very low clock jitter specifications thus increasing power consumption and silicon area for the clock generation and distribution.
The main problem with the present solutions for filtering ADCs is that they do not solve the right problem. The present solutions present an energy efficient solution in the medium frequency range (5 . . . 20 MHz), but for wider bandwidths the frequency and phase response of the main ADC affects the total filtering response thus rendering the design very difficult and increasing current consumption. On the other hand, at narrower bandwidths, there is already enough noise shaping in the main ADC so that noise shaping boost of the merged filter is not required.
Another problem with the current solutions is the limited usability with very wide filter bandwidths in respect to the ADC sampling frequency i.e. with low oversampling ratio, OSR.